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submitted 3 months ago by GustavoM@lemmy.world to c/riscv@lemmy.world
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submitted 6 months ago by GustavoM@lemmy.world to c/riscv@lemmy.world

Title. Just curious since apparently risc-v is mentioned as a "ultra low power draw" CPU... so I'd like to know if that is true. Thanks in advance.

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RISC-V Wants All Your Cores (semiengineering.com)
submitted 7 months ago by merthyr1831@lemmy.world to c/riscv@lemmy.world

RISC-V intl. announces plans to add matrix multiplication to the ISA, in an attempt to turn the architecture into a general-purpose solution for all processor derivatives eg. GPUs, TPUs, DSPs, Security Processors, Power management processors.

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submitted 7 months ago by merthyr1831@lemmy.world to c/riscv@lemmy.world

This isn't a rip on RISC-V but it's something I notice a lot with ARM and RISC SBCs compared to x86, which seems to support Linux, Windows, MacOS regardless of the device specs.

On other platforms, the developers have to build special iso images for each device, even though the underlying OS supports the whole architecture.

If I wanted to move to a new device (say, upgrade my Raspberry pi 4B to an Orange Pi, or other RISC-V alternatives) I'd have to ensure the new device had support from my OS choice, download a new image for it, and manually port stuff across. (as far as I can tell).

What's the technical reason that x86 can configure the OS on the fly but ARM/RISC can't?

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submitted 8 months ago by demesisx@infosec.pub to c/riscv@lemmy.world

Abstract. Formal languages are commonly used to model the seman- tics of instruction set architectures (e.g. ARM). The majority of prior work on these formal languages focuses on concrete instruction execu- tion and validation tasks. We present a novel Haskell-based modelling approach which allows the creation of flexible and versatile architecture models based on free monads and a custom expression language. Con- trary to existing work, our approach does not make any assumptions regarding the representation of memory and register values. This way, we can implement non-concrete software analysis techniques (e.g. sym- bolic execution where values are SMT expressions) on top of our model as interpreters for this model. In contrast to prior work, our modelling approach is therefore explicitly focused on the creation of custom ISA in- terpreters. We employ our outlined approach to create an abstract model and a concrete interpreter for the RISC-V base instruction set. Based on this model, we demonstrate that custom interpreters can be implemented with minimal effort using dynamic information flow tracking as a case study.

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submitted 8 months ago by 3arn0wl@lemmy.world to c/riscv@lemmy.world

This seems to be a good summary of the recent RISC-V conference in China.

Top quotes from the article :

Data shows that by 2022, the cumulative shipment of RISC-V chips worldwide reached 10 billion.

According to Counterpoint Research's prediction, by 2025, the cumulative shipment of RISC-V processors will exceed 80 billion units, with a compound annual growth rate (CAGR) of 114.9%. By then, RISC-V will account for 14% of the global CPU market, 28% of the IoT market, 12% of the industrial market, and 10% of the automotive market.

According to research firm Semico, the number of RISC-V chips is expected to grow by a CAGR of 73.6% from 2023 to 2027, producing approximately 25 billion AI chips based on the RISC-V, with revenues reaching $291 billion.

Beijing Open Source Chip (BOSC) announced the second generation "XiangShan", an open-source high-performance RISC-V processor core, which has surpassed ARM A76 in performance... "Nanhu" architecture has completed "productization transformation"... In 2022, two companies have applied "Xiangshan-Nanhu". One of them has taped out the chips and will receive samples in September this year, and another will tape out in the second half of this year.

The third-generation "Kunminghu" architecture is under development, and its performance can be comparable to ARM Neoverse N2. Xiangshan-Kunminghu has a chance to reach the level of high-performance processor cores of ARM two or three years ago, but it is only in terms of performance. Its area and power consumption, where ARM has a strong advantage, still need to be optimized.

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submitted 9 months ago by cyph3rPunk@infosec.pub to c/riscv@lemmy.world

Sipeed Lichee Pi 4A RISC-V SBC review and Debian demo. This is the first RISC-V computer I’ve tested that's provided a usable desktop computing experience right out of the box. End-user RISC-V is starting to arrive! :)

You can learn more about the Lichee Pi 4A on its web page here: https://sipeed.com/licheepi4a

And the board has excellent documentation here: https://wiki.sipeed.com/licheepi4a.html

Note that the hardware I used in this video was purchased from AliExpress: https://www.aliexpress.com/item/10050...

I have reviewed four previous RISC-V SBCs, including the StarFive VisionFive 2, which also (after some messing around) provides a good desktop experience:

• VisionFive 2: RISC-V Quad Core Low Co...

I also have an 2023 update on RISC-V developments here:

• RISC-V 2023 Update: From Embedded Com...

And my general introduction to RISC-V is here:

• Explaining RISC-V: An x86 & ARM Alter...

For additional ExplainingComputers videos and other content, you learn about becoming a channel member here:

/ @explainingcomputers

More videos on computing and related topics can be found at:

/ @explainingcomputers

You may also like my ExplainingTheFuture channel at:

/ @explainingthefuture

Chapters: 00:00 Introduction 00:45 Unboxing 03:33 Specifications 07:26 First Boot 10:37 Debian Demo 18:10 Another Milestone

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submitted 9 months ago by 3arn0wl@lemmy.world to c/riscv@lemmy.world
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submitted 9 months ago by 3arn0wl@lemmy.world to c/riscv@lemmy.world
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submitted 10 months ago by rist097@lemmy.world to c/riscv@lemmy.world
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submitted 10 months ago by rist097@lemmy.world to c/riscv@lemmy.world
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submitted 11 months ago by rist097@lemmy.world to c/riscv@lemmy.world
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submitted 11 months ago by rist097@lemmy.world to c/riscv@lemmy.world

Somebody made a list of RiscV SBCs

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submitted 11 months ago by zik@lemmy.world to c/riscv@lemmy.world

“My belief is in the next 5 to 10 years, RISC-V will take over all the data centers,” Keller told EE Times

RiscV

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